FIG. 1 is a block diagram illustrating a basic design flow for fabricating an ASIC. The design flow includes a front-end design process that creates a logical design for the ASIC, and a back-end design process that creates a physical design for the ASIC. The front-end design process begins with providing a design entry 10 for an electronic circuit that is used to generate a high-level electronic circuit description, which is typically written in a Hardware Description Language (HDL) 12.
Interconnect statistical data 14 is used to create a wire load model 16, which defines the resistance, capacitance, and the area of all nets in the design. The statistically generated wire load model 16 is used to estimate the wire lengths in the design and define how net delays are computed. The HDL 12 and the wire load model 16 are then input into a logic synthesis tool 18 to generate a list of logic gates and their interconnections, called a “netlist” 20. Next, system partitioning is performed in step 22 in which the physical design is partitioned to define groupings of cells small enough to be timed accurately with wire load models 16 (local nets). The resulting design typically includes many cells with many interconnect paths. A prelayout simulation is then performed in step 24 with successive refinement to the design entry 10 and to logic synthesis 18 to determine if the design functions properly.
After prelayout simulation 24 is satisfactory, a layout tool 25 is used to create physical layout of the design begining with floorplanning in step 26 in which the blocks of the netlist 20 are arranged on the chip. The location of the cells in the blocks are then determined during a placement process in step 28. A routing process makes connections between cells and blocks in step 30. Thereafter, circuit extraction determines the resistance and capacitance of the interconnects in step 32. A postlayout simulation is then performed in step 34 from which the overall timing and performance of the chip can be determined, with successive refinement to floorplanning 26 as necessary.
In today's semiconductor industry, customers contract with chip manufacturers to design and produce highly customized integrated circuit designs. During the design flow of a custom integrated circuit design, it is not uncommon for the customer to request changes to the design, especially after postlayout simulation 34. The customer may request changes after post layout simulation 34 using two methods. One method is to submit engineering change orders (ECO) to the manufacturer who then inputs the ECOs 54 into the layout tool 25 to apply the changes to the layout. The second method is for the customer to incorporate the changes into a copy of the netlist 20, and submit the modified netlist 48 to the manufacturer. The manufacturer then inputs the modified netlist 48 into the layout tool 25, which applies the changes in the modified netlist 48 into the existing layout database.
Both methods for implementing customer changes in a design layout to suffer disadvantages. The first method where the customer submits ECOs 54 to the manufacturer requires hand-generation of net-list based ECO information, followed by an automation that checks the validity of the hand-generated ECO information. Hand generating ECOs 54 is error-prone to. In addition, there needs to be a checker to validate the hand-generated information, which adds an additional cumbersome step is the layout process flow.
In the second method, the layout tool 25 must create a new layout from the modified netlist 48, and then compares the two layouts to determine what changes need to be made to the existing layout. This can be problematic because the manufacturer cannot determine what the ECOs 54 are until the modified layout 50s built and compared to the original layout. In addition, the current approach compares two layouts, which is both time-consuming and costly. This existing approach is also said to be cumbersome to work with and in some cases does not work correctly.
The present invention provides an improved method for optimizing the netlist-based ECO flow for rapid design turnaround time.